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<div class="content-intro"><p><img src="https://i.imgur.com/XN94Hg4.png" alt="" width="900" style="max-width: 100%;"></p>
<p> </p></div><p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Role</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}"> </span></strong></p>
<p><span data-contrast="auto">The Senior Systems Software Engineer will be a member of the core team building the Quantum Key Distribution system. The focus is on high-performance Python services on Linux, algorithm optimization and acceleration (also via hardware offload), and the role spans defining software architecture, integrating with FPGA/embedded subsystems, and turning requirements into reliable, observable software. </span><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="auto">The Senior Systems Software Engineer leads and co-owns the overall </span><span data-contrast="auto">internal QKD </span><span data-contrast="auto">software architecture and client-facing software API. By setting engineering standards, mentoring, and unblocking delivery, they ensure predictable releases and a strong execution cadence.</span><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Responsibilities</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}"> </span></strong></p>
<p><span data-contrast="auto">The Senior Systems Software Engineer should expect to work in the following activities.</span><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">System architecture</span>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Leading and co-owning the QKD software architecture: control plane services, key sifting/postprocessing integration, configuration management, monitoring, and external interfaces </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Defining module boundaries and service APIs; evolving the system toward clear data/control-plane separation<span data-ccp-props="{}"> </span></li>
</ul>
</li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Efficient implementation and hardware/software integration</span>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Designing and implementing high-performance Python services on Linux (asyncio, WebSockets, NumPy); profiling and tuning for latency and throughput</li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Developing, profiling, and optimizing <span data-contrast="auto">QKD sifting and postprocessing algorithms</span><span data-contrast="auto"> (signal handling/processing, error correction/information reconciliation, LDPC, privacy amplification) to maximize key rate and minimize end-to-end latency; applying algorithmic improvements and implementation techniques (vectorization, concurrency/async, memory/layout tuning, C/C++ extensions, SIMD/CUDA/GPU/FPGA offload where appropriate)</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Defining and maintaining robust interfaces with embedded/FPGA system components over UART/USB/PCIe/Ethernet; respecting realtime constraints and failure modes </li>
<li data-leveltext="" data-font="Symbol" data-listid="3"
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