Senior FPGA Developer (SystemVerilog)

<div class="content-intro"><p><img src="https://i.imgur.com/XN94Hg4.png" alt="" width="900" style="max-width: 100%;"></p> <p>&nbsp;</p></div><p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Role</span></span><span data-ccp-props="{&quot;134245418&quot;:true,&quot;134245529&quot;:true,&quot;335559738&quot;:160,&quot;335559739&quot;:80}">&nbsp;</span></strong></p> <p><span data-contrast="auto">The Senior FPGA Developer&nbsp;will be a member of the core team building the&nbsp;Quantum Key Distribution&nbsp;system. The focus is end</span><span data-contrast="auto">‑</span><span data-contrast="auto">to</span><span data-contrast="auto">‑</span><span data-contrast="auto">end RTL ownership on AMD/Xilinx (Artix</span><span data-contrast="auto">‑</span><span data-contrast="auto">7,&nbsp;Kintex&nbsp;UltraScale): architect,&nbsp;implement,&nbsp;verify, and close timing on high</span><span data-contrast="auto">‑</span><span data-contrast="auto">rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and&nbsp;mentors&nbsp;a junior engineer.</span><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring</span><span data-contrast="auto">‑</span><span data-contrast="auto">up, and deliver reproducible, versioned bitstreams.</span><span data-ccp-props="{}">&nbsp;</span></p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Responsibilities</span></span><span data-ccp-props="{&quot;134245418&quot;:true,&quot;134245529&quot;:true,&quot;335559738&quot;:160,&quot;335559739&quot;:80}">&nbsp;</span></strong></p> <p><span data-contrast="auto">The Senior FPGA Developer should expect to work&nbsp;in&nbsp;the following activities.</span><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">RTL architecture, interfaces, and&nbsp;rather high-speed&nbsp;datapaths</span> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1">Owning SystemVerilog RTL architecture/implementation for Artix<span data-contrast="auto">‑</span><span data-contrast="auto">7 and&nbsp;Kintex&nbsp;UltraScale&nbsp;(SystemVerilog,&nbsp;Vivado)</span></li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1">Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third<span data-contrast="auto">‑</span><span data-contrast="auto">party MAC/PCS IP</span></li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1">Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low<span data-contrast="auto">‑</span><span data-contrast="auto">level protocols&nbsp;—&nbsp;</span> <span data-contrast="auto">and bridging them to high</span><span data-contrast="auto">‑</span><span data-contrast="auto">throughput interfaces (DDR/PCIe)</span></li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1">Defining clear AXI/AXI<span data-contrast="auto">‑</span><span data-contrast="auto">Stream boundaries and register maps for SW/FW integration</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Constraints, timing closure, and&nbsp;floorplanning</span> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="2" data-aria-level="1">Authoring and