وصف الوظيفة
<div class="content-intro"><p><img src="https://i.imgur.com/XN94Hg4.png" alt="" width="900" style="max-width: 100%;"></p>
<p> </p></div><p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Role</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}"> </span></strong></p>
<p><span data-contrast="auto">The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end</span><span data-contrast="auto">‑</span><span data-contrast="auto">to</span><span data-contrast="auto">‑</span><span data-contrast="auto">end RTL ownership on AMD/Xilinx (Artix</span><span data-contrast="auto">‑</span><span data-contrast="auto">7, Kintex UltraScale): architect, implement, verify, and close timing on high</span><span data-contrast="auto">‑</span><span data-contrast="auto">rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer.</span><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="auto">The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring</span><span data-contrast="auto">‑</span><span data-contrast="auto">up, and deliver reproducible, versioned bitstreams.</span><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Responsibilities</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}"> </span></strong></p>
<p><span data-contrast="auto">The Senior FPGA Developer should expect to work in the following activities.</span><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">RTL architecture, interfaces, and rather high-speed datapaths</span>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Owning SystemVerilog RTL architecture/implementation for Artix<span data-contrast="auto">‑</span><span data-contrast="auto">7 and Kintex UltraScale (SystemVerilog, Vivado)</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third<span data-contrast="auto">‑</span><span data-contrast="auto">party MAC/PCS IP</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low<span data-contrast="auto">‑</span><span data-contrast="auto">level protocols — </span> <span data-contrast="auto">and bridging them to high</span><span data-contrast="auto">‑</span><span data-contrast="auto">throughput interfaces (DDR/PCIe)</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Defining clear AXI/AXI<span data-contrast="auto">‑</span><span data-contrast="auto">Stream boundaries and register maps for SW/FW integration</span><span data-ccp-props="{}"> </span></li>
</ul>
</li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Constraints, timing closure, and floorplanning</span>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Authoring and
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